Field of the Invention
The invention relates to a lateral high-voltage sidewall transistor.
German Patent No. DE 43 09 764 C2 discloses a conventional lateral high-voltage transistor in which the drain drift path is formed of an n-conducting region in which one or more p-conductive regions are embedded.
It is an object of the invention to provide a lateral high-voltage sidewall transistor which has a good conductivity and which can withstand high voltages and which can be easily fabricated.
With the foregoing and other objects in view there is provided, in accordance with the invention, a lateral high-voltage sidewall transistor configuration, including:
a low-doped semiconductor substrate of a first conductivity type;
a low-doped epitaxial layer of a second conductivity type disposed on the semiconductor substrate;
first semiconductor layers of the first conductivity type and second semiconductor layers of the second conductivity type, the first and second semiconductor layers being disposed in an alternating configuration in the epitaxial layer;
a source region of the second conductivity type extending through the first and second semiconductor layers as far as the semiconductor substrate;
a drain region of the second conductivity type extending through the first and second semiconductor layers as far as the semiconductor substrate;
the epitaxial layer being formed with a gate trench;
a gate electrode including a gate insulating layer lining the gate trench and including a conductive material filling the gate trench, the gate electrode extending through the first and second semiconductor layers as far as the semiconductor substrate and being disposed adjacent to the source region and extending in a direction toward the drain region;
the source region and the gate trench each having at least one side; and
a semiconductor region of the first conductivity type disposed on the at least one side of the source region and the gate trench, the semiconductor region extending as far as the semiconductor substrate and extending under the source region and extending partially under the gate insulating layer.
In other word, the object of the invention is achieved by a lateral high-voltage sidewall transistor in which alternating semiconductor layers of the one conductivity type and of the other conductivity type are provided on a low-doped semiconductor substrate of the other conductivity type, in which furthermore a source region of the one conductivity type and a drain region of the one conductivity type each extend through the semiconductor layers as far as the semiconductor substrate, in which a gate electrode including a gate trench provided with a gate insulating layer and filled with conductive material likewise extends through the semiconductor layers as far as the semiconductor body and is provided adjacent to the source region in the direction of the drain region, and in which, at least on one side of the source region and the gate trench, a semiconductor region of the other conductivity type is provided, extending as far as the semiconductor substrate and extending under the source region and also extending partially under the gate electrode.
The conductivity of this sidewall transistor increases with the number of pairs of such semiconductor layers having alternating conductivity types.
The one conductivity type (second conductivity type) is preferably the n conductivity type. The other conductivity type (first conductivity type) is thus the p conductivity type, and the semiconductor substrate is therefore pxe2x88x92-doped.
During the production of the lateral high-voltage sidewall transistor according to the invention, first of all semiconductor layers with alternately opposite conductivity types are applied to the entire area of a semiconductor substrate, for example a pxe2x88x92-doped semiconductor substrate. This can preferably be done by a number of epitaxial depositions and subsequent ion implantations. However, it is also possible, with the aid of the SOI technique (SOI=silicon on insulator) to use as the semiconductor substrate an oxidized silicon wafer, onto which, with the aid of the direct-wafer-bonding technique, the semiconductor layers having alternating conductivity types are then applied. For this purpose, the so-called smart cut technique with subsequent epitaxial deposition can also be applied, if appropriate, in which thin layers of a first semiconductor wafer are transferred to a second semiconductor wafer by direct bonding.
The area density of the n doping, for example phosphorus, and of the p doping, for example boron, in the semiconductor layers should not exceed about 1012 cmxe2x88x922 when silicon is used as the semiconductor material, that is to say should not lie above the xe2x80x9cbreakdown concentrationxe2x80x9d. If silicon carbide (SiC) is used as the semiconductor material, then an area density of the n doping or the p doping in the semiconductor layers of about 1013 cmxe2x88x922 should be aimed at, but the density should not exceed this value.
For producing the transistor configuration, first of all a structure is produced in which n-doped and p-doped semiconductor layers are applied one after another to a weakly pxe2x88x92-doped semiconductor body, the semiconductor layers not exceeding an area density for the doping of the order of magnitude of 1012 cmxe2x88x922 for silicon and 1013 cmxe2x88x922 for silicon carbide.
Trenches for the source and drain regions and for the body region are introduced into the structures produced in this way. An n dopant, for example phosphorus or arsenic, is then diffused into the surrounding semiconductor material from the walls of the trenches for the source region and the drain region. In a similar way, a p dopant, that is to say for example boron, is made to diffuse from the walls of the body trench into the surrounding semiconductor material. Following this diffusion, the respective trenches for source, drain and body can be filled up with doped polycrystalline silicon, in order in this way to form feed lines to the individual levels of the semiconductor layers. These feed lines can be separated from one another by an insulating layer of silicon dioxide, for example. If appropriate, it is also possible to reinforce the polycrystalline silicon further with a conductive material.
After the production of the source region, the drain region and the p-conductive semiconductor region, performed in the above manner by diffusion from the respective trenches, the gate trenches are introduced and coated or lined with an insulating layer of silicon dioxide, for example. The gate trenches are then filled up with n+-conductive polycrystalline silicon.
Contact is therefore made with the n-conductive semiconductor layers along the drift path through the source region and drain region, that is to say the semiconductor layers are connected via the respective trenches for the source electrode and the gate electrode. In a similar way, the p-conductive semiconductor layers of the drift path are connected through the p-conductive semiconductor region and respectively the body trench.
The position of the source region and p-conductive semiconductor region, as indicated above, means that the source regions are interrupted by the p-conductive semiconductor region, and a channel zone is produced in which the current can flow along the trench wall of the gate trench when there is a positive gate-source voltage.
The lateral high-voltage sidewall transistor according to the invention can, if necessary, also be equipped with a field plate, which has a distance from the semiconductor layers which increases continuously or step by step in the direction from source to drain and is embedded in an insulating layer which, for example, is formed of silicon dioxide or silicon nitride.
The drain region is expediently enclosed by the source region at a distance of the drift path. This does not apply to an implementation of the lateral high-voltage sidewall transistor in the SOI technique already mentioned. Here, the source region and drain region are preferably provided parallel to each other. The trenches are then etched through the entire epitaxial region as far as the insulating oxide.
When a field plate is used, the n doping should predominate in the drift path, so that preferably, in addition to respective pairs of semiconductor layers of alternating conductivity type, there is a further n-conductive layer with an area doping concentration in the range of 1012 cmxe2x88x922, without an associated p-conductive layer.
In accordance with another feature of the invention, a source region of a further, second lateral high-voltage sidewall transistor is provided adjacent to a first lateral high-voltage sidewall transistor such that the source regions are separated by the semiconductor region of the first conductivity type.
In accordance with yet another feature of the invention, the expitaxial layer and the first and second semiconductor layers are doped such that the epitaxial layer together with the first and second semiconductor layers have an overall n-doping which is higher than an overall p-doping.
In accordance with a further feature of the invention, the first and second semiconductor layers are epitaxial, ion-implanted layers.
In accordance with another feature of the invention, the first and second semiconductor layers are produced by wafer bonding with an oxidized silicon wafer.
Although it was assumed above that the one conductivity type is the n conductivity type and the other conductivity type is the p conductivity type, if appropriate, the converse conductivity types can also be provided.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a lateral high-voltage sidewall transistor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.